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Design Methodology of SHA2 Hardware Accelerator
MA Zhangang, LI Tingting, CAO Xixin
Acta Scientiarum Naturalium Universitatis Pekinensis    2022, 58 (6): 1007-1014.   DOI: 10.13209/j.0479-8023.2022.086
Abstract419)   HTML    PDF(pc) (2711KB)(157)       Save
In view of difficulty of SHA2 hardware acceleration, a novel performance-improving scheme of SHA2 hardware accelerator is put forth with the following techniques adopted. 1) Using 4K bits Ping-Pong buffer storing padded message block, the Message Padding Unit and Hash Calculation Unit can work in parallel as two stages of two-stage pipeline. 2) In Hash Calculation Unit, computations which have no dependency on iterative computation are extracted from two folded rounds of hash transformation as pre-computation unit and can work concurrently with post-computation unit in the form of two-stage pipeline rather than pseudo-pipeline which was proposed in the previous researches. 3) 3:2/4:2 compressors without carry chain and fast adders are adopted in pre-computation unit and post-computation unit to shorten critical path greatly. The proposed scheme also supports double hash computation which directs digest result of source data to the entry of hash iteration unit to obtain final result of double hash of SHA2, improving the performance of SHA2 hardware accelerator.
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A BFGS-Corrected Gauss-Newton Solver for Bundle Adjustment
ZHAO Shuaihua, LI Yanyan, CAO Jian, CAO Xixin
Acta Scientiarum Naturalium Universitatis Pekinensis    2020, 56 (6): 1013-1019.   DOI: 10.13209/j.0479-8023.2020.098
Abstract1494)   HTML    PDF(pc) (609KB)(236)       Save
Aiming at the problem that the Gauss-Newton (GN) method is sensitive to the initial information matrix in the Bundle Adjustment (BA) model, which leads to limited application scenarios, the paper proposes a novel method BFGS-GN using BFGS (Broyden-Fletcher-Goldfarb-Shanno) algorithm to improve the traditional Gauss-Newton method. When the information matrix of the Gauss-Newton method loses positive definiteness, BFGS algorithm can be used to modify the normal equations, which fundamentally eliminates the mathematical defect that the Gauss-Newton method is sensitive to initial values. Experimental results demonstrate that proposed method is robust to different types of initials. The same accuracy and the number of iterations as GN can be obtained when the initial values are good. As for bad inputs, GN-based BA method cannot work but BFGS-GN can converge to a minimum.
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Design and Implementation of an Asynchronous Low Power RSA Circuit Structure
ZHANG Qihui, CAO Jian, CAO Xixin, YU Dunshan, ZHANG Xing
Acta Scientiarum Naturalium Universitatis Pekinensis    2018, 54 (6): 1351-1354.   DOI: 10.13209/j.0479-8023.2018.046
Abstract818)   HTML    PDF(pc) (2003KB)(206)       Save

An asynchronous low power RSA circuit structure and its modular multiplication circuit structure for smart cards and RFID tags are proposed. By using GTECH optimization scheme and BrzCallMux implementation strategy, ASIC implementation is carried out based on a TSMC 130 nm standard CMOS technology. Experimental results show that the area of the proposed asynchronous low power RSA is only 4% of that of another asynchronous RSA, its average time to perform a cryptographic operation is only 0.216% of that of another asynchronous RSA, and its power consumption is only 16.99% of that of its corresponding synchronous counterpart.

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A Novel Algorithm for the Video Caption Extraction
CAO Xixin,LIU Jing,YANG Xudong,WU Shuai,ZHANG Qihui
Acta Scientiarum Naturalium Universitatis Pekinensis   
Abstract739)      PDF(pc) (3048KB)(330)       Save
The authors propose a novel algorithm for the video caption extraction. By using the image sharpening method, a better extraction effect can be achieved for the special video sequences. The caption area and the non-caption area can be efficiently separated by neighborhood average operation. A projection algorithm is proposed to implement on a better decomposition and extraction based on the statistical characteristics, and this can efficiently separate the caption area and make the extraction coordinates more precise. The experiments show that the proposed algorithm has a better effect compared with the original methods. Because of the low computational complexity, it can be widely used in the field of video image processing.
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A Novel Algorithm for Video Zooming
CAO Xixin,LIU Jing,WU Shuai,ZHANG Qihui,LIN Jinlong,WANG Ping
Acta Scientiarum Naturalium Universitatis Pekinensis   
Abstract758)      PDF(pc) (843KB)(283)       Save
Inspired from the quantum mechanics, the authors propose a novel and practical video zooming algorithm which has a better image quality than other methods. Compared to the quantum mechanics models , an image is treated as a energy field and modify the traditional cardinal spline function. This method reduces the sample effect across the edges and improves the human pleasure. The proposed method has a low complexity, and keeps the coherence between frames for video sequence. It is especially suit for the embedded equipments such as mobile phones and PDAs.
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A Novel Parallel VLSI Architecture for H.264/AVC Scalar Quantization
PENG Chungan,YU Dunshan,CAO Xixin,SHENG Shimin
Acta Scientiarum Naturalium Universitatis Pekinensis   
Abstract594)            Save
52-level scalar quantization technology plays an important role in H.264/AVC. A novel parallel VLSI architecture is proposed for its hardware implementation, in which the 4×4 matrix multiplications is replaced by 16 unsigned compressed shift-adder-trees using partial CSD code scheme, switching reference wirings substitutes for look-up operation, and division is also avoided effectively, and no ROM or RAM is adopted in the overall quantizer. It can fulfill all the quantization calculations for all H.264 hybrid transform in 4×4 block parallelism. Its block throughput can reach 121.6MHz, which can meet the real-time requirement for 4096×2304@120Hz (119.43936M/s) video compression. Compared with the conventional architecture, 38% cost and 30% power are saved. Considering speed and cost optimization, this architecture is very suitable for pipeline acceleration, and it is a useful IP for high resolution H.264 encoder VLSI realization.
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The VLSI Implementation of Intra Prediction in H.264/AVC
ZHU Zhongping,FENG Jianhua,Cao Xixin
Acta Scientiarum Naturalium Universitatis Pekinensis   
Abstract651)            Save
An intra prediction circuit in H.264/AVC is implemented. By choosing variable circuit path and reusing adders, the authors implement all the prediction modes except plane prediction mode with low cost. Synthesized by SMIC 0.18 μm CMOS technology, the total gates is about 4000, the critical path delay is 5.7 ns.
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A Low Complexity H.264 VBSME Architecture for Wireless Video Communication Applications
PENG Chungan,YU Dunshan,CAO Xixin,SHENG Shimin
Acta Scientiarum Naturalium Universitatis Pekinensis   
Abstract678)            Save
An efficient low complexity H.264 VBSME (variable-block-size motion estimation) VLSI (very large scale integrated) architecture is designed, in which a MB-size input buffer, 17×16 snake scan register array, 8×8 PE array,4×4 SAD-adder-tree are used and a four-step VBS MV generator structure is proposed to reduce the hardware cost for wireless video communication applications. Compared with the MB-level VBSME structure, the total count of gates is reduced to 37%, the delay of critical path is shorten from 9.8 ns to 8.2 ns, and nearly 50.3% power is saved and the main data-path width is narrowed to 25%, but all MB characters are reserved. Its low-hardware-complexity performance makes it suitable for the integration of H.264 encoder in wireless video communication applications.
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Realization of 6, Tap Finite Impulse Response Interpolation Filter for H.264/AVC Encoder
WANG Qingchun,CAO Xixin,LU Weijun,HE XiaoyanCAO Jian
Acta Scientiarum Naturalium Universitatis Pekinensis   
Abstract637)            Save
It is proposed that four hardware architectures of 6, tap finite impulse response interpolation filter for the design of H.264/AVC encoder (SOC). Moreover, based on comparative analysis of Synopsys Design Compiler to implement the hardware at the same constraint, an efficient half pixel interpolation filter (6, tap FIR) architecture had been given finally.
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